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GS9091B genlinx? ii 270mb/s dese rializer for sdi and dvb-asi 1 of 71 proprietary & confidential GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi www.gennum.com data sheet 38910 - 2 july 2008 key features ? smpte 259m-c compliant de scrambling and nrzi to nrz decoding (with bypass) ? dvb-asi 8b/10b decoding ? integrated cable equalizer ? 500m typical equalization of belden 1694a cable ? integrated line-based fifo for data alignment/delay, clock phase interchange, dvb-asi data packet extraction and clock rate interchange, and ancillary data packet extraction ? integrated vco and reclocker ? user selectable additional processing features including: ? trs, anc data checksum, and edh crc error detection and correction ? programmable anc data detection ? illegal code remapping ? internal flywheel for noise immune h, v, f extraction ? automatic standards detection and indication ? enhanced gennum serial peripheral interface (gspi) ? jtag test interface ? polarity insensitive for dvb-asi and smpte signals ? +1.8v core power supply with optional +1.8v or +3.3v i/o power supply ? small footprint (11mm x 11mm) ? low power operation (typically 350mw) ? pb-free and rohs compliant applications ? smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the GS9091B is a 270mb/s equali zing and reclocking dese- rializer with an internal fifo. it provides a complete re- ceive solution for sd-sdi and dvb-asi applications. in addition to equalizing, reclocking and deserializing the input data stream, the GS9091B performs nrzi -to-nrz de- coding, descrambli ng as per smpte 259m-c, and word alignment when operating in smpte mode. when operat- ing in dvb-asi mode, the device will word align the data to k28.5 sync characte rs and 8b/10b deco de the received stream. the integrated equalizer is optimized for 270mb/s and can typically equalize up to 500m of belden 1694a cable. both the equalizer and the internal reclocker are fully compati- ble with both smpte and dvb-asi input streams. the GS9091B includes a range of data processi ng functions such as edh support (error detection and handling), and automatic standards detection. the device can also detect and extract smpte 352m payload identifier packets and in- dependently identify the received video standard. this in- formation is read from inte rnal registers via the host interface port. the GS9091B also inco rporates a video line-based fifo. this fifo may be used in four user-selectable modes to car- ry out tasks such as data alignment / delay, clock phase in- terchange, mpeg packet extraction and clock rate interchange, and ancillary data packet extraction. parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal op- erating at 27mhz. the device may also be used in a low-latency data pass through mode where only descrambling and word align- ment will be performed in smpte mode.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 2 of 71 proprietary & confidential functional block diagram GS9091B functional block diagram reclocker s->p smpte de- scramble, word alignment and flywheel dout[9:0] carrier_detect reset asi sync detect host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo ddi ddi data_error power on reset jtag_en trs check csum check anc data detection dvb-asi word alignment and 8b/10b decode trs correct csum correct edh check & correct illegal code re- map dvb_asi pll_lock lf+ lb_cont pclk locked lock detect smpte_bypass smpte sync detect lf- auto/man programmable i/o stat[3:0] fifo fw_en ioproc_en rd_clk rd_reset equalizer eq_bypass
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 3 of 71 proprietary & confidential revision history contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagram ..................................... .................................................................. .......................2 1. pin out..................................................................................................................... ..........................................5 1.1 pin assignment............................................................................................................. ......................5 2. electrical characteristics .................................................................................................. ....................... 12 2.1 dc electrical characteristics ....... ....................................................................................... ........ 12 2.2 ac electrical characterist ics .............................................................................................. ........ 14 2.3 solder reflow profiles..................................................................................................... .............. 16 2.4 host interface map......................................................................................................... ................ 17 2.4.1 host interface map (r/w register s) ........... ........... ........... ........... .......... ......... ......... ..... 19 2.4.2 host interface map (read only registers) .................................................................. 21 3. detailed description........................................................................................................ .......................... 23 3.1 functional overview........................................................................................................ ............. 23 3.2 cable equalization ......................................................................................................... ................ 24 3.3 clock and data recovery .............. ........... ........... ........... ........... ........... ........... ........... ......... ......... 24 3.3.1 internal vco and phase detector................................................................................ 24 3.4 serial-to-parallel conversion .............................................................................................. ...... 24 3.5 modes of operation ......................................................................................................... ............. 24 3.5.1 lock detect .............................................................................................................. ............ 25 3.5.2 auto mode................................................................................................................ ............ 27 3.5.3 manual mode .............................................................................................................. ........ 27 3.6 smpte functionality ........................................................................................................ ............. 28 3.6.1 smpte descrambling and word alignment ............................................................ 28 3.6.2 internal flywheel ........................................................................................................ ...... 28 3.6.3 switch line lock handling............................................................................................. 29 3.6.4 hvf timing signal generation ..................................................................................... 30 3.7 dvb-asi functionality ...................................................................................................... ........... 31 version ecr pcn date changes and/or modifications 0 139930 november 2006 new document. 1 144807 april 2007 converting to data sheet. modified electrical characteristics . 2 150199 50711 july 2008 dvb_asi operation specification change in auto mode.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 4 of 71 proprietary & confidential 3.7.1 dvb-asi 8b/10b decoding............................................................................................. 32 3.7.2 status signal outputs .................................................................................................... ... 32 3.8 data-through functionality ................................................................................................. ...... 32 3.9 additional processing features ............................................................................................. .... 33 3.9.1 fifo load pulse .......................................................................................................... ....... 33 3.9.2 ancillary data detection and indication................................................................... 34 3.9.3 edh packet detection..................................................................................................... .35 3.9.4 edh flag detection....................................................................................................... .... 36 3.9.5 smpte 352m payload identifier................................................................................... 39 3.9.6 automatic video standard and data format detection ...................................... 40 3.9.7 error detection and indication ..................................................................................... 41 3.9.8 additional smpte mode processing ........................................................................... 46 3.10 internal fifo operation ................................................................................................... ......... 49 3.10.1 video mode .............................................................................................................. ......... 49 3.10.2 dvb-asi mode ............................................................................................................ ..... 51 3.10.3 ancillary data extraction mode ................................................................................ 54 3.10.4 bypass mode............................................................................................................. ........ 56 3.11 parallel data outputs..................................................................................................... ............. 57 3.11.1 parallel data bus output buffers ............................................................................... 57 3.11.2 parallel output in smpte mode..................... ............................................................ 58 3.11.3 parallel output in dvb-asi mode............................................................................. 58 3.11.4 parallel output in data-through mode......... .......................................................... 58 3.12 programmable multi-function outputs............................................................................... 58 3.13 GS9091B low-latency mode .................................................................................................. .. 60 3.14 gspi host interface....................................................................................................... ............... 61 3.14.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 61 3.14.2 data read and write timing ....................................................................................... 62 3.14.3 configuration and status registers........................................................................... 64 3.15 jtag operation ............................................................................................................ ................. 65 3.16 device power up........................................................................................................... ............... 66 4. references & relevant standards ............................................................................................. ............ 67 5. application information ..................................................................................................... ..................... 68 5.1 typical application circuit ................................................................................................ ......... 68 6. package & ordering information .............................................................................................. ............ 69 6.1 package dimensions......................................................................................................... ............. 69 6.2 packaging data............................................................................................................. ................... 70 6.3 marking diagram............................................................................................................ ................ 70 6.4 ordering information....................................................................................................... ............. 70
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 5 of 71 proprietary & confidential 1. pin out 1.1 pin assignment figure 1-1: pin assignment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k locked pclk lb_ cont vbg dout9 dout8 dout0 dout7 dout6 dout5 dout4 dout2 dout1 jtag_en io_vdd io_vdd io_gnd io_vdd core _vdd core _gnd core _gnd data_ error fw_en dvb_asi smpte_ bypass nc heat_ sink_ gnd sdin _tdi sclk _tck sdout _tdo cs_ tms nc nc nc nc ana_ vdd nc nc nc nc term sdi ioproc _en reset vco_ vdd lf+ pll_ vdd eq_gnd agc+ rd_clk stat2 nc nc fifo_en auto/ man lf- pll_ gnd vco_ gnd ana_ vdd nc nc ana_ gnd ana_ gnd io_gnd io_gnd core _gnd core _gnd io_gnd heat_ sink_ gnd io_gnd core _gnd io_gnd io_vdd nc core _gnd dout3 heat_ sink_ gnd sdi heat_ sink_ gnd io_gnd core _gnd io_gnd nc core _gnd nc eq_vdd heat_ sink_ gnd heat_ sink_ gnd nc nc nc nc rd_ reset eq_ bypass core _vdd stat3 agc- nc stat0 stat1
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 6 of 71 proprietary & confidential table 1-1: ball list and description ball name timing ty p e description a1 lf+ analog input loop filter component connection. connect to lf- through a 4.4nf capacitor. a2, b5, c3, c4, c5, c6, c7, c9, d3, d8, d9, e3, e8, f8, g8, g9, h4, h5, h6, h7, k2 nc C C no connect. not connected internally. a3 lb_cont analog input control signal input control voltage to fine-tune the loop bandwidth of the pll. a4 vco_vdd analog input power power supply connection for voltage-controlled-oscillator. connect to +1.8v dc. a5 vbg analog input bandgap filter capacitor. connect to gnd as shown in typical application circuit . a6 fifo_en non synchronous input contol signal input signal levels are lvcmos / lvttl compatible. used to enable / disable the internal fifo. when fifo_en is high, the internal fifo will be enabled. data will be clocked out of the device on the rising edge of the rd_clk input pin if the fifo is in video mode or dvb-asi mode. when fifo_en is low, the internal fifo is bypassed and parallel data is clocked out on the rising edge of the pclk output. a7 auto/man non synchronous input control signal input signal levels are lvcmos / lvttl compatible. when set high, the GS9091B will operate in auto mode. the s mpte_bypass pin becomes an output status signal set by the device. in this mode, the GS9091B will automatically detect, reclock, deserialize, and process smpte compliant input data. when set low, the GS9091B will operate in manual mode. the dvb_asi and smpte_bypass pins become input control signals. in this mode, the application layer must set these two external pins for the correct reception of either smpte or dvb-asi data. manual mode also supports the reclocking and deserializing of data not conforming to smpte or dvb-asi streams. a8 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. the locked pin will be high whenever the device has correctly received and locked to smpte compliant data in smpte mode or dvb-asi compliant data in dvb-asi mode, or when the reclocker has achieved lock in data-through mode. it will be low otherwise. when the pin is low, all digital output signals will be forced to logic low levels. a9 pclk C output pixel clock output signal levels are lvcmos / lvttl compatible. 27mhz parallel clock output.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 7 of 71 proprietary & confidential a10, b10, c10, d10, e10, f10, g10, h10, j10, k10 dout[9:0] synchronous with rd_clk or pclk output parallel video data bus signal levels are lvcmos / lvttl compatible. when the internal fifo is enabled and configured for either video mode or dvb-asi mode, parallel data will be clocked out of the device on the rising edge of rd_clk. when the internal fifo is in bypass mode, parallel data will be clocked out of the device on the rising edge of pclk. dout9 is the msb and dout0 is the lsb. b1 lf- analog input loop filter component connection. connect to lf+ through a 4.4nf capacitor. b2 pll_vdd analog input power power supply connection for phase-locked loop. connect to +1.8v dc. b3 pll_gnd analog input power ground connection for phase-locked loop. connect to gnd. b4 vco_gnd analog input power ground connection for voltage-controlled-oscillator. connect to gnd. b6 fw_en non synchronous input contol signal input signal levels are lvcmos / lvttl compatible. used to enable or disable the noise immune flywheel of the device. when set high, the internal flywheel is enabled. this flywheel is used in the extraction of timing signals, the generation of trs signals, the automatic detection of video standards, and in manual switch line lock handling. when set low, the internal flywh eel is disabled. timing based trs errors will not be detected. b7, j6 core_vdd non synchronous input power power supply for digital logic blocks. connect to +1.8v dc. b8 smpte_bypass non synchronous input / output control signal input / status signal output signal levels are lvcmos / lvttl compatible. this pin is an input set by the application layer in manual mode, and an output set by the device in auto mode. auto mode (auto/man = high): the smpte_bypass pin will be high only when the device has locked to a smpte compliant data stream. it will be low otherwise. when the pin is low, no i/o processing features are available. manual mode (auto/man = low): when the application layer sets this pin high in conjunction with dvb_asi = low, the device will be configured to operate in smpte mode. all i/o processing features may be enabled in this mode. when smpte_bypass is set low, the device will not support the descrambling, decoding, or word alignment of received smpte data. no i/o processing features will be available. table 1-1: ball list and description (continued) ball name timing ty p e description
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 8 of 71 proprietary & confidential b9 dvb_asi non synchronous input / output control signal input / status signal output signal levels are lvcmos / lvttl compatible. this pin and its function are only supported in manual mode (auto/man = low). when the application layer sets this pin high, the device will be configured to operate in dvb-asi mode. the smpte_bypass pin will be ignored. when set low, the device will not support the decoding or word alignment of received dvb-asi data. c1, c2 ana_vdd analog input power power supply connection for anal og core. connect to +3.3v dc. c8, e9, f9, h8 io_vdd non synchronous input power power supply for digital i/o. for a 3.3v tolerant i/o, connect pins to either +1.8v dc or +3.3v dc. for a 5v tolerant i/o, connect pins to a +3.3v dc. d1, d2 ana_gnd analog input power ground connection for analog core. connect to gnd. d4, d5, e4, e5, f4, f5, g4, g5 core_gnd non synchronous input power ground connection for digital logic blocks. connect to gnd. d6, d7, e6, e7, f6, f7, g6, g7 io_gnd non synchronous input power ground connection for digital i/o. connect to gnd. e1 eq_gnd analog input power ground connection for equalizer core. connect to gnd. e2 term analog input termination for serial digital input. ac couple to ana_gnd f1, g1 sdi, sdi analog input serial digital differential input pair. f2, f3, g2, g3, h2, h3 heat_sink_gnd analog input power heat sink connection. connect to main ground plane of application board. h1 eq_vdd analog input power power supply connection for equa lizer core. connect to +3.3v dc. h9 rd_reset synchronous with rd_clk input fifo read reset signal levels are lvcmos / lvttl compatible. valid input only when the device is in smpte mode (smpte_bypass = high and dvb-asi = low), and the internal fifo is configured for video mode ( section 3.10.1 ). a high to low transition will reset the fifo pointer to address zero of the memory. j1, k1 agc+, agc- analog input external agc capacitor connection. connect j1 and k1 together through a 1uf capacitor. table 1-1: ball list and description (continued) ball name timing ty p e description
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 9 of 71 proprietary & confidential j2 eq_bypass analog input contol signal input signal levels are 3.3v cmos / lvttl compatible. equalizer bypass. when eq_bypass is high, the equalizer stages are bypassed. when eq_bypass is low, normal operation of the equalizer stages resumes. j3 jtag_en non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sclk_tck, sdout_tdo, and sdin_tdi are configured for jtag boundary scan testing. when set low, cs _tms, sclk_tck, sdout_tdo, and sdin_tdi are configured as gspi pins for normal host interface operation. j4 cs _tms synchronous with sclk_tck input control signal input signal levels are lvcmos / lvttl compatible. chip select / test mode select host mode (jtag_en = low): cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag_en = high): cs _tms operates as the jtag test mode select, tms, and is active high. j5 sdout_tdo synchronous with sclk_tck output control signal input signal levels are lvcmos / lvttl compatible. serial data output / test data output host mode (jtag_en = low): sdout_tdo operates as the host interface serial output, sdout, used to read status and conf iguration information from the internal registers of the device. jtag test mode (jtag_en = high): sdout_tdo operates as the jtag test data output, tdo. j7 data_error synchronous with pclk output status signal output. signal levels are lvcmos / lvttl compatible. the data_error pin will be low when an error within the received data stream has been detected by the device. this pin is an inverted logical oring of all detectable errors listed in the internal error_status register. once an error is detected, data_error will remain low until the start of the next video frame / field, or until the error_status register is read via the host interface. the data_error pin will be high when the received data stream has been detected without error. note: it is possible to program which error conditions are monitored by the device by se tting appropriate bits in the error_mask register high. all error conditions are detected by default. table 1-1: ball list and description (continued) ball name timing ty p e description
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 10 of 71 proprietary & confidential k3 ioproc_en non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to enable or disable the i/o processing features. when set high, the following i/o pr ocessing features of the device are enabled: ? illegal code remapping ? edh crc error correction ? ancillary data checksum error correction ? trs error correction ? edh flag detection to enable a subset of these features, keep ioproc_en high and disable the individual feature(s) in the ioproc_disable register accessible via the host interface. when set low, the device will enter low-latency mode. note: when the internal fifo is configured for video mode or ancillary data extraction mode, ioproc_en must be set high (see section 3.10 ). k4 reset non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to reset the internal operat ing conditions to default setting or to reset the jtag test sequence. host mode (jtag_en = low): when asserted low, all functional blocks will be set to default conditions and all input and output signals become high impedance. when set high, normal operatio n of the device resumes 10usec after the low-to-high transition of the reset signal. jtag test mode (jtag_en = high): when asserted low, all functional blocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operatio n of the jtag test sequence resumes. k5 sclk_tck non synchronous input control signal input signal levels are lvcmos / lvttl compatible. serial data clock / test clock. all jtag / host interface address and data are shifted into/out of the device synchronously with this clock. host mode (jtag_en = low): sclk_tck operates as the host interface serial data clock, sclk. jtag test mode (jtag_en = high): sclk_tck operates as the jtag test clock, tck. table 1-1: ball list and description (continued) ball name timing ty p e description
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 11 of 71 proprietary & confidential k6 sdin_tdi synchronous with sclk_tck input control signal input signal levels are lvcmos / lvttl compatible. serial data input / test data input host mode (jtag_en = low): sdin_tdi operates as the host interfa ce serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag_en = high): sdin_tdi operates as the jtag test data input, tdi. k7, k8, j8, j9 stat[0:3] synchronous with pclk or rd_clk output multi function i/o port signal levels are lvcmos / lvttl compatible. programmable multi-function outpu ts. by programming the bits is the io_config register, each pin can output one of the following signals: ?h ?v ?f ?fifo_ld ?anc ? edh_detect ? fifo_full ? fifo_empty these pins are set to certain default values depending on the configuration of the device and the internal fifo mode selected. see section 3.12 for details. k9 rd_clk C input fifo read clock signal levels are lvcmos / lvttl compatible. the application layer clocks the parallel data out of the fifo on the rising edge of rd_clk. table 1-1: ball list and description (continued) ball name timing ty p e description
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 12 of 71 proprietary & confidential 2. electrical characteristics 2.1 dc electrical characteristics table 2-1: absolute maximum ratings parameter value/units supply voltage core -0.3v to +2.1v supply voltage i/o -0.3v to +3.47v input voltage range (lf+, lf-, lb_cont, vbg) -0.5v to +2.3v input voltage range (sdi, sdi , agc+, agc-, eq_bypass) -0.5v to +3.6v input voltage range (all other) -0.5v to +5.25v ambient operating temperature -20c < t a < 85c storage temperature -40c < t stg < 125c esd protection on all pins (see note 1) 1kv notes: 1. mil std 883 esd protection will be applied to all pins on the device. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the ac/dc electrical characteristic sections is not implied. table 2-2: dc electrical characteristics v dd = 1.8v 5%, 3.3v 5%; t a = 0c to 70c, unless otherwise specified. typical values: v cc = 1.8v, 3.3v and t a =25c parameter symbol condition min ty p max units notes system operating temperature range t a C 0 25 70 c 1 core power supply voltage core_vdd C 1.71 1.8 1.89 v C analog core power supply voltage ana_vdd C 3.13 3.3 3.47 v C digital i/o buffer power supply voltage io_vdd 1.8v operation 1.71 1.8 1.89 v C io_vdd 3.3v operation 3.13 3.3 3.47 v C pll power supply voltage pll_vdd C 1.71 1.8 1.89 v C vco power supply voltage vco_vdd C 1.71 1.8 1.89 v C equalizer power supply voltage eq_vdd C 3.13 3.3 3.47 v C core supply current i dd total 1.8v supply C 64 80 ma 2 total 3.3v supply C 69 92 ma 3
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 13 of 71 proprietary & confidential i/o supply current i io i/o supply, 1.8v operation C4.58ma4 i/o supply, 3.3v operation C8.514ma4 power dissipation p d core_vdd = 1.8v io_vdd = 1.8v C 350 C mw C core_vdd = 1.89v io_vdd = 3.47v C C 490 mw C digital i/o input voltage, logic low v il 1.8v operation or 3.3v operation C C 0.35 x io_vdd vC input voltage, logic high v ih 1.8v operation or 3.3v operation 0.65 x io_vdd CCvC output voltage, logic low v ol i ol = 8ma @ 3.3v, 4ma @ 1.8v CC0.4vC output voltage, logic high v oh i ol = -8ma @ 3.3v, -4ma @ 1.8v io_vdd - 0.4 CCvC eq_bypass input voltage v il logic low C C 0.8 v C v ih logic high 2.4 C C v C serial digital inputs input common mode voltage v cmin t a = 25c C 1.75 C v C input resistance C single ended C 1.64 C k C notes 1. all dc and ac electrical parameters within specification. 2. maximum supply current at t a = 0c and v dd = 1.89v supply. 3. maximum supply current at t a = 75c and v dd = 3.47v supply. 4. i/o currents are based on output drivers driving one cmos load. table 2-2: dc electrical characteristics (continued) v dd = 1.8v 5%, 3.3v 5%; t a = 0c to 70c, unless otherwise specified. typical values: v cc = 1.8v, 3.3v and t a =25c parameter symbol condition min ty p max units notes
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 14 of 71 proprietary & confidential 2.2 ac electrical characteristics table 2-3: ac electrical characteristics v dd = 1.8v 5%, 3.3v 5%; t a = 0c to 70c, unless otherwise specified. typical values: v cc = 1.8v, 3.3v and t a =25c parameter symbol condition min ty p max units notes system input voltage swing v sdi t a =25c, differential 720 800 950 mv p-p 1 lock time (asynchronous switch) t lock t a =25c, 500m of belden 1694a C 560 C us 2 serial digital input serial input data rate dr sdi C C 270 C mb/s C dvb-asi payload data rate dr asi 204 byte mode C C 213.9 mb/s 3,5 188 byte mode C C 213.7 mb/s 4,5 achievable cable length C belden 1694a cable 270mhz C 500 C m C input return loss C C 15 C C db 6 input capacitance C single ended C 1 C pf C parallel output parallel output clock frequency f pclk CC27CmhzC parallel output clock duty cycle dc pclk C40C60%C variation of parallel output clock (from 27mhz) C device unlocked t a = 5c to 45c -7 C +7 % 7 output data hold time t oh with 15pf load 3.0 C C ns 8 output delay time t od with 15pf load C C 10.0 ns 8 gspi gspi input clock frequency f gspi C C C 54.0 mhz C gspi clock duty cycle dc gspi C40C60%C gspi setup time t gs C1.5CCnsC
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 15 of 71 proprietary & confidential gspi hold time t gh C1.5CCnsC notes 1. 0m cable length. 2. time from input no-data to data switch and lock ed pin set high. 3. transmission format includes 204 byte data packets preceded by two k28.5 synchronization charac ters. payload data rate exclud es the two k28.5 synchronization characters. 4. transmission format includes 188 byte data packets preceded by two k28.5 synchronization charac ters. payload data rate exclud es the two k28.5 synchronization characters. 5. maximum payload is achieved vi a data packet mode,however, any combination of burst and packet mode is supported as long as ea ch byte or packet is preceded by two k28.5 characters. 6. 5mhz to 270mhz. 7. when the serial input to the GS9091B is removed, the pclk out put signal will continue to operat e at 27mhz and the internal vc o will remain at this frequency within +/-7% over the range 5 o c to 45 o c. over the full opera ting temperature range (0 o c to 70 o c), the vco may deviate from 27mhz up to +/-13%. 8. timing includes the following outputs: dout[9:0], h, v, f, anc, edh_detect, fifo_full, fifo_empty, fifo_ld , worderr, syncout. when the fifo is enabled, the outputs are measured with respect to rd_clk. table 2-3: ac electrical characteristics (continued) v dd = 1.8v 5%, 3.3v 5%; t a = 0c to 70c, unless otherwise specified. typical values: v cc = 1.8v, 3.3v and t a =25c parameter symbol condition min ty p max units notes
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 16 of 71 proprietary & confidential 2.3 solder reflow profiles the device is manufactured with matte-sn terminations and is compatible with both standard eutectic and pb-free solder reflow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-1 . the recommended standard eutectic reflow profile is shown in figure 2-2 . figure 2-1: maximum pb-free solder reflow profile (preferred) figure 2-2: standard eutectic solder reflow profile 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 17 of 71 proprietary & confidential 2.4 host interface map table 2-4: host interface map register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifo_ld_position[12:0] 28h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 27h 26h error_mask_register 25h not used not used not used not used not used not used not used not used not used vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_ mask sav_err_ mask eav_err _mask ff_pixel_end_f1[12:0] 24h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f1[12:0] 23h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_end_f0[12:0] 22h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f0[12:0] 21h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f1[12:0] 20h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f1[12:0] 1fh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f0[12:0] 1eh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f0[12:0] 1dh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f1[10:0] 1ch not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f1[10:0] 1bh not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f0[10:0] 1ah not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f0[10:0] 19h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f1[10:0] 18h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f1[10:0] 17h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f0[10:0] 16h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f0[10:0] 15h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure4[10:0] 14h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure3[12:0] 13h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 18 of 71 proprietary & confidential raster_structure2[12:0] 12h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure1[10:0] 11h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 video_format_out_b(4,3) 10h vfo4-b7 vfo4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo 4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3-b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo 3-b1 vfo3-b0 video_format_out_a(2,1) 0fh vfo2-b7 vfo2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo 2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1-b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo 1-b1 vfo1-b0 anc_type(5)[15:0] 0ehb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(4)[15:0] 0dhb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(3)[15:0] 0chb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(2)[15:0] 0bhb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(1)[15:0] 0ahb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_line_b[10:0] 09h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 anc_line_a[10:0] 08h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 fifo_full_offset 07h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fifo_empty_offset 06h not used not used not used not used anc_ data_ delete not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 io_config 05h not used not used not used anc_ data_ switch stat3_ config b2 stat3_ config b1 stat3_ config b0 stat2_ config b2 stat2_ config b1 stat2_ config b0 stat1_ config b2 stat1_ config b1 stat1_ config b0 stat0_ config b2 stat0_ config b1 stat0_ config b0 data_format 04h not used not used not used not used edh_ flag_ update ap_crc_ v ff_crc_v edh_ detect version_ 352m not used not used std_ lock data_ format b3 data_ format b2 data_ format b1 data_ format b0 edh_flag_out 03h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh edh_flag_in 02h not used anc-ues _in anc-ida _in anc-idh _in anc-eda _in anc-edh _in ff-ues_in ff-ida_in ff-idh_in ff-eda_i n ff-edh_i n ap-ues_i n ap-ida_i n ap-idh_i n ap-eda_i n ap-edh_i n error_status 01h not used not used not used not used not used not used not used not used not used vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err sav_err eav_err ioproc_disable 00h not used not used not used not used not used not used anc_pkt _ext fifo_ mode b1 fifo_ mode b0 h_ config not used not used illegal_ remap edh_crc _ins anc_ csum_ ins trs_in note: addresses 02ch to 42bh store the cont ents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ). table 2-4: host interface map (continued) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 19 of 71 proprietary & confidential 2.4.1 host interface map (r/w registers) table 2-5: host interface map (r/w registers) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifo_ld_position[12:0] 28h b12b11b10b9b8b7b6b5b4b3b2b1b0 27h 26h error_mask_register 25h vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_ mask sav_err_ mask eav_err _mask ff_pixel_end_f1[12:0] 24h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f1[12:0] 23h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_end_f0[12:0] 22h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f0[12:0] 21h b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f1[12:0] 20h b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f1[12:0] 1fh b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f0[12:0] 1eh b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f0[12:0] 1dh b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f1[10:0] 1ch b10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f1[10:0] 1bh b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f0[10:0] 1ah b10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f0[10:0] 19h b10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f1[10:0] 18h b10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f1[10:0] 17h b10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f0[10:0] 16h b10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f0[10:0] 15h b10b9b8b7b6b5b4b3b2b1b0 14h 13h 12h
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 20 of 71 proprietary & confidential 11h 10h 0fh anc_type(5)[15:0] 0eh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(4)[15:0] 0dh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(3)[15:0] 0ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(2)[15:0] 0bh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(1)[15:0] 0ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_line_b[10:0] 09h b10b9b8b7b6b5b4b3b2b1b0 anc_line_a[10:0] 08h b10b9b8b7b6b5b4b3b2b1b0 fifo_full_offset 07h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fifo_empty_offset 06h anc_ data_ delete b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 io_config 05h anc_ data_ switch stat3_ config b2 stat3_ config b1 stat3_ config b0 stat2_ config b2 stat2_ config b1 stat2_ config b0 stat1_ config b2 stat1_ config b1 stat1_ config b0 stat0_ config b2 stat0_ config b1 stat0_ config b0 data_format 04h edh_ flag_ update 03h 02h 01h ioproc_disable 00h anc_pkt _ext fifo_ mode b1 fifo_ mode b0 h_ config illegal_ remap edh_crc _ins anc_ csum_ ins trs_in note: addresses 02ch to 42bh store the cont ents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ). table 2-5: host interface map (r/w registers) (continued) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 21 of 71 proprietary & confidential 2.4.2 host interface map (read only registers) table 2-6: host interface map (read only registers) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh 1eh 1dh 1ch 1bh 1ah 19h 18h 17h 16h 15h raster_structure4[10:0] 14h b10b9b8b7b6b5b4b3b2b1b0 raster_structure3[12:0] 13h b12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure2[12:0] 12h b12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure1[10:0] 11h b10b9b8b7b6b5b4b3b2b1b0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 22 of 71 proprietary & confidential video_format_out_b(4,3) 10h vfo4-b7 vfo4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo 4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3-b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo 3-b1 vfo3-b0 video_format_out_a(2,1) 0fh vfo2-b7 vfo2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo 2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1-b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo 1-b1 vfo1-b0 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h data_format 04h ap_crc_ v ff_crc_v edh_ detect version_ 352m std_ lock data_ format b3 data_ format b2 data_ format b1 data_ format b0 edh_flag_out 03h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh edh_flag_in 02h not used anc-ues _in anc-ida _in anc-idh _in anc-eda _in anc-edh _in ff-ues_in ff-ida_in ff-idh_in ff-eda_i n ff-edh_i n ap-ues_i n ap-ida_i n ap-idh_i n ap-eda_i n ap-edh_i n error_status 01h vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err sav_err eav_err 00h note: addresses 02ch to 42bh store the cont ents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ). table 2-6: host interface map (read only registers) (continued) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 23 of 71 proprietary & confidential 3. detailed description ? functional overview ? cable equalization ? clock and data recovery ? serial-to-parallel conversion ? modes of operation ? smpte functionality ? dvb-asi functionality ? data-through functionality ? additional processing features ? internal fifo operation ? parallel data outputs ? programmable multi-function outputs ? GS9091B low-la tency mode ? gspi host interface ? jtag operation ? device power up 3.1 functional overview the GS9091B is a 270mb/s equalizing and recloc king deserializer with an internal fifo and programmable multi-func tion output port. the device has two basic modes of operation. in auto mode, the GS9091B can au tomatically detect sm pte data streams at its input. in manual mode, the device can be set to process smpte or dvb/asi data streams. the digital signal processing core handles ancillary data detection/indication, error detection and handling (edh), smpte352m extraction, and automatic video standards detection. these features are all enabled by de fault, but may be indi vidually disabled via internal registers accessible through the gspi host interface. the provided programmable multi-function output pins may be configured to output various status signals including h, v, an d f timing, ancillary data detection, edh detection, and a fifo load pulse. the inte rnal fifo supports 4 modes of operation, which may be used for data alignment, data delay, mpeg packet ex traction, or ancillary data extraction. the GS9091B contains a jtag interface fo r boundary scan test implementations.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 24 of 71 proprietary & confidential 3.2 cable equalization the input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. the serial data signal may be connected to the input pins (sdi/sdi ) in either a differential or single ended configuration. ac coupling of the inputs is recommended, as the sdi and sdi inputs are internally biased at approximately 1.8v. the cable equalization block is powered by the eq_vdd and eq_gnd pins. the cable equalizer can be bypassed by setting the eq_bypass pin high. 3.3 clock and data recovery the GS9091B contains an integrat ed clock and data re covery block. the function of this block is to lock to the input data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. the operating centre frequency of the reclocker is 270mb/s. 3.3.1 internal vco and phase detector the GS9091B uses an internal vco and pfd as part of the reclocker' s phase-locked loop. each block requires a +1.8v dc power supply, which is supplied via the vco_vdd / vco_gnd and pll_vdd / pll_gnd pins. 3.4 serial-to-parallel conversion the function of this block is to extract 10-bit parallel data words from the reclocked serial data stream and simultaneously present them to the smpte and dvb-asi word alignment blocks. 3.5 modes of operation the GS9091B has two basic modes of operatio n: auto mode and manual mode. auto mode is enabled when auto/man is set high, and manual mode is enabled when auto/man is set low. as indicated in figure 3-1 . dvb_asi and data through are only supported in manual mode. in auto mode (auto/man = high), the GS9091B will au tomatically detect, equalize, reclock, deserialize, and process smpte 259m-c input data. in manual mode (auto/man = low), the smpte_bypass and dvb_asi pins must be set as per table 3-2 for the correct reception of either smpte or dvb-asi data. manual mode also suppor ts the equalizing, reclocking and deserializing of 270mb/s data not conforming to smpte or dvb-asi streams.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 25 of 71 proprietary & confidential figure 3-1: GS9091Bs modes of operation 3.5.1 lock detect once the reclocker has locked to the received serial digital data stream, the lock detect block of the GS9091B searches for the appropriate sync words, and indicates via the locked output pin when the device has su ccessfully achieved lock. the locked pin is designed to be stable. it will not toggle during the locking process, nor will it glitch during a smpte synchronous switch. the lock detection process is summarized in figure 3-2 . gs9091 manual mode (section 3.6.3) data-through functionality (section 3.9) auto mode (section 3.6.2) smpte functionality (section 3.7) dvb-asi functionality (section 3.8) smpte functionality (section 3.7)
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 26 of 71 proprietary & confidential figure 3-2: lock detection process the lock detection algorithm ( figure 3-2 ) first determines if the input is a 270m b/s serial digital data stream. when the serial data input signal is considered invalid, the locked pin will be set low, and all device outputs will be forced low, except pclk. if a valid serial digital input signal has been detected, and the device is in auto mode, the lock algorithm will attempt to detect the presence of smpte trs words. assuming that a valid 270mb/s smpte signal has been applie d to the device, the locked pin will be set high. power up or reset no yes (device in manual mode) valid serial digital input? internal reclocker locked? device in auto mode? (section 3.6.2) smpte trs words detected? smpte_bypass and dvb_asi pins must be set to support different functionalities (section 3.6.3). sets smpte_bypass pin low device device sets locked pin low device sets locked pin high device sets smpte_bypass status pin (section 3.6.2) device outputs accurate 27mhz clock on pclk pin device outputs 27mhz +/- 7% clock on pclk pin device sets all other output pins low (input data invalid) yes no no no yes yes
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 27 of 71 proprietary & confidential for serial inputs that do not conform to smpte or dvb-asi formats, the device can achieve the locked state in manual mode. in auto mode, the locked signal will be asserted low, the parallel outputs wi ll be latched to lo gic low, and the smpte_bypass output signal will also be set low. in manual mode, the smpte_bypass and dvb_asi input pins must be set low. if the GS9091B achieves lo ck to the input data signal, data will be passed directly to the parallel outputs without any further processing (see section 3.8 ). 3.5.2 auto mode the GS9091B is in auto mode when the auto/man input pin is set high. in this mode, smpte_bypass becomes an output stat us pin, as shown in table 3-1 . 3.5.3 manual mode the GS9091B is in manual mode when the auto/man input pin is set low. in this mode, the smpte_bypass and dvb_asi pins become input signals, and the operating mode of the device is set by these pins as shown in table 3-2 . table 3-1: auto mode output status signals pin settings format smpte_bypass sd smpte high not smpte low table 3-2: manual mode input status signals pin settings format smpte_bypass dvb_asi sd smpte high low dvb-asi x high not smpte or dvb-asi (data-through mode)* low low *note: see section 3.8 for more detail on data-through mode
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 28 of 71 proprietary & confidential 3.6 smpte functionality the GS9091B is in smpte mode once the device has dete cted two smpte trs sync words. the GS9091B will remain in smpte mode until six smpt e trs sync words fail to be detected. trs word detection is a continuous process, and the device will identify both 8-bit and 10-bit trs words. in auto mode, the GS9091B sets the smpte_bypass pin high to indicate that it has locked to a smpte input data stream. when operating in manual mode, the dvb_asi pin must be set low and the smpte_bypass pin must be set high in order to enable smpte operation. 3.6.1 smpte descrambling and word alignment the GS9091B performs nrzi-to-nrz decodi ng, descrambling ac cording to smpte 259m-c, and word alignment of the data to the trs sync words when in smpte mode. note: when 8-bit data is embedded into the smpte signal, the source must have the two lsbs of the 10-bit stream set to logic low in order for word alignment to function correctly. 3.6.2 internal flywheel the GS9091B has an internal fl ywheel for the genera tion of internal / external timing signals, the detection and correction of certain error conditions, and the automatic detection of video standards. the flywheel is only operational in smpte mode. the flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the trs id words of the received video stream. the flywheel maintains information about the total line length, active line length, total number of lines per field / frame, and total active li nes per field / frame fo r the received video stream. full synchronization of the flywheel to the received video standard therefore requires one complete video frame. once synchronization has been achieved, the flywheel will continue to monitor the received trs timing information to maintain synchronization. the fw_en input pin controls the synchronization mechanism of the flywheel. when this input signal is low, the flywheel wi ll re-synchronize all pixel and line based counters on every received trs id word. when fw_en is set to logic high, re-synchronization occurs when the flywheel detects three to four consecutive video lines containing mistimed trs information. this provides a measure of noise immunity to internal and external timing signal generation. the flywheel will be disabled if the device loses lock, or a low-to-high transition occurs on the reset pin.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 29 of 71 proprietary & confidential 3.6.3 switch line lock handling the principle of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timing and alignment of the stream, whereas the vertical timing remains in synchronization. 3.6.3.1 automatic switch line lock handling the GS9091B also implements automatic switch line lock handling. by utilizing both the synchronous switch point defined in smpte rp168, and the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point. this will occur whether or not the de vice has detected trs word errors. word alignment re-synchronization will also take place at this time. automatic switch line lock ha ndling will occur regardless of the setting of the fw_en pin. the switch line is defined as follows: ? for 525 line interlaced systems: re-syn c takes place at the end of lines 10 & 273 ? for 625 line interlaced systems: re-syn c takes place at the end of lines 6 & 319 a full list of 270mb/s video standard s and switching lines is shown in table 3-3 . at every pclk cycle the device samples the fw_en pin. when the fw_en pin is set low anywhere within the active line, the fl ywheel will re-synchroni ze immedi ately to the next trs word. 3.6.3.2 manual switch line lock handling the ability to manually re-synchronize the flywheel is also impo rtant when switching asynchronous sources or to implement other non-standardized video switching functions. to account for the horizontal disturbance caused by a synchronous switch, it is necessary to re-synchronize the flywheel immediately after the switch has taken place. rapid re-synchroni zation of the GS9091B to the new vi deo standard can be achieved by disabling the flywheel (setting the fw_en pin to logic low) after the switch, and re-enabling the flywheel after the next trs word. table 3-3: switch line position for 270mb/s digital systems system video format sampling signal standard parallel interface serial interface switch line number sdti 720x576/50 (2:1) 4:2:2 bt.656 bt.656 + 305m 259m-c 6, 319 720x483/59.94 (2:1) 4:2:2 125m 125m + 305m 259m-c 10, 273 525 720x483/59.94 (2:1) 4:2:2 125m 125m 259m-c 10, 273 625 720x576/50 (2:1) 4:2:2 bt.656 125m 259m-c 6, 319
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 30 of 71 proprietary & confidential 3.6.4 hvf timing signal generation the GS9091B extracts timing pa rameters, and outputs them to the f, v and h pins, from either the received trs signals (fw_en = low) or from the internal flywheel-timing generator (fw_en = high). horizontal blanking period (h), vertical blan king period (v), and field odd / even timing (f) are extracted and are available for output on any of the multi-function output port pins, if so programmed (see section 3.12 ). the h signal timing is configurable via the h_config bit of the internal ioproc_disable register as either active line-based blanking, or trs-based blanking (see table 3-14 in section 3.9.8 ). active line-based blanking is enabled when the h_config bit is set low. in this mode, the h output is high for the entire horizontal blanking period, including the eav and sav trs words. this is the defaul t h timing used by the device. when h_config is set high, trs based blanking is enabled. in this case, the h output will be high for the entire horizontal blanking period as indicated by the h bit in the received trs id words. the timing of these signals is shown in figure 3-3 . note 1: when the internal fifo is configur ed for video mode, the h, v, and f signals will be timed to the data output from the fifo (see section 3.10.1 ). note 2: when the GS9091B is configured fo r low-latency mo de, the h, v, and f output timing will be trs-based as shown in section 3.13 . active line-based timing is not available in this mode, and the setting of the h_config host interface bit will be ignored. figure 3-3: h,v,f timing y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 31 of 71 proprietary & confidential 3.7 dvb-asi functionality dvb_asi functionality is only supported in manual mode. in manual mode, the dvb_asi pin must be set to logic high in order to enable dvb-asi operation. the smpte_bypass pin will be ignored. when using dvb-asi mode, the use of application circuit in figure 3-4 on page 31 is suggested. the use of this application circuit will prevent the internal pll from false locking to a dvb-asi signal harmonic ra ther than the 270mhz fundamental. this application circuit will detect the false lock state and restart the on-chip pll. the application circuit does this by detecting if the lock has been de-asserted for longer than ~700 s, and if so resets the pll by discharging the loop filter capacitor through a cmos switch. the applications circuit be low show how this can be implemented by using a stg719 switch as a reference. other low leakage cmos switches may also be substituted within the circuit. figure 3-4: GS9091B false lock restart circuit the circuit above can be implemented using either a small state machine in an fpga or general purpose i/o on a microcontroller in combination with some firmware. typically, a system using the GS9091B will have an existing fpga and/or microcontroller that may have some spare i/o that can be used to implement the false lock restart circuit. the choice of method will depend on what spare system resources are available. in either case, the waveform shown in figure 3-5 on page 31 represents how the pll restart must be driven. the delay values of 700 s and 20 s are nominal but the values can be longer. in the case where the sdi inputs are not driven with a valid dvb-asi signal, the restart_pll signal should be repeated indefinitely as long as locked remains de-asserted. figure 3-5: GS9091B false lock restart circuit waveforms of false lock after power-up and false lock after a signal switch. fpga or microcontroller gpio gs9090b GS9091B l ocked in out lf+ lf- d s1 in s2 1 6 2 5 3 4 stg719 5 6 1 stg719 restart_pll ddi power_ok locked restart_pll ~700s ~20s ~700s ~20s valid dvb-asi input signal valid dvb-asi input signal
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 32 of 71 proprietary & confidential 3.7.1 dvb-asi 8b/10b decoding the GS9091B will word align the data to the k28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. note: dvb-asi sync words must be immediat ely followed by an mpeg packet header for word alignment to correctly function. the extracted 8-bit data will be presented to dout [7:0], bypassing all internal smpte mode data processing. 3.7.2 status signal outputs in dvb-asi mode, the dout9 and dout8 pins will be configured as dvb-asi status signals worderr and syncout respectively. syncout will be high whenever a k28.5 sync character is present on the output. worderr will be high whenever the device has detected an illegal 8b/10b code word or there is a running disparity error. 3.8 data-through functionality the GS9091B may be configured to operate as a simple serial-to-pa rallel converter. in this mode, the data is output to the parallel output without performing any decoding, descrambling, or word-alignment. data-through functionality is enabled when the auto/man , smpte_bypass , and dvb_asi input pins are set to logic low. under these conditions, the GS9091B allows 270mb/s input data not conforming to smpte or dvb-asi streams to be reclocked and deserialized. if the device is in data-throu gh mode, and the reclocker locks to the data stream, the locked pin will be representative of the serial digital input data frequency.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 33 of 71 proprietary & confidential 3.9 additional processing features the GS9091B contains additional processing features that are available in smpte mode only (see section 3.6 ). 3.9.1 fifo load pulse to aid in the implementation of auto-phasing and line synchronization functions, the GS9091B will generate a fifo load pulse to reset line-based fifo storage. this fifo_ld signal is available for output on one of the multi-function output port pins, if so programmed (see section 3.12 ). the fifo_ld pulse is an active low signal which will assert low for one pclk period, generating a fifo write reset signal. this signal is co-timed to the sav xyz code word present on the output data bus. this ensures that the next pclk cycle will correspond with the first active sample of the video line. note: when the internal fifo of the GS9091B is set to operate in video mode, the fifo_ld pulse can be used to drive the rd_reset input to the device (see section 3.10.1 ). figure 3-6 shows the default timing relationship between the fifo_ld signal and the output video data. figure 3-6: fifo_ld pulse timing 3.9.1.1 programmable fifo load position the position of the fifo_ld pulse can be moved in pclk increments from its default position at the sav xyz code word to a maximum of one full line from the default position. the offset number of pclk's must be programmed in the fifo_ld_position[12:0] inte rnal register (address 28h), via the host interface. the fifo_ld_position[12:0] register is designed to accommodate the longest sd line length. if a value greater than the maximum line length at the operating sd standard is programmed in this register, the fifo_ld pulse will not be generated. after a device reset, the fifo_ld_position[12:0] register is set to zero and the fifo_ld pulse will assume the default timing. 000 3ff 000 xyz y'cbcr data pclk fifo_ld
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 34 of 71 proprietary & confidential 3.9.2 ancillary data de tection and indication the GS9091B will detect a ll types of ancillary data in eith er the vertical or horizontal data spaces. the anc status signal is provided to indicate the position of ancillary data in the output data stream. this signal is available for output on the multi-function output port pins (see section 3.12 ). the anc status signal is synchronous with pclk and can be used as a clock enable to external logic, or as a write enable to an external fifo or other memory device. the anc signal will be asserted high whenever ancillary data is detected in the video data stream (see figure 3-7 ). both 8-bit and 10-bit ancillary data preambles will be detected by the GS9091B. note: when the internal fifo is configured for video mode, the anc signal will be timed to the data output from the fifo (see section 3.10.1 ). figure 3-7: anc status signal 3.9.2.1 programmable ancillary data detection the GS9091B will detect a ll types of ancillary data by defa ult. in addition , up to five different ancillary data types can be programmed for detection. this is accomplished by programming the anc_type registers with the did and/or sdid values, via the host interface, for each data type to be detected (see table 3-4 ). the GS9091B will compare the received did and/or sdid with th e programmed values and assert anc only if an exact match is found. if the did or sdid values are set to zero in the anc_type register, a comparison or match for that codeword will not be made. for example, if the did is programmed but the sdid is set to zero, the device will detect all ancillary data types matching the did value, regardless of the sdid. if both di d and sdid values are non-zero, then the received ancillary data type must match both the did and sdid case s before the device will assert anc high. in the case where all five did and sdid valu es are set to zero, th e GS9091B will detect all ancillary data types. this is the default setting after a device reset. if greater than one, but less than five, did and/or sdid values have been programmed, then only those matching ancillary data types will be detected and indicated. note: see smpte 291m for a defini tion of ancillary data terms. 3ff 000 3ff did dbn dc anc data anc data csum blank anc y'cbcr data pclk
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 35 of 71 proprietary & confidential 3.9.3 edh packet detection the GS9091B will determine if edh packets ar e present in the inco ming video data and assert the edh_detect output status signal appropriately. edh_detect will be set high when edh packets have been detected and will remain high until edh packets are no longer present. the signal will be set low at the end of the vertical blanking (falling edge of v) if an edh packet has not been received and detected during vertical blanking. edh_detect can be programmed to be available for output on the multi-function output port pins (see section 3.12 ). the edh_detect bit is also available in the data_format register at address 04h (see table 3-7 ). table 3-4: host interface description for programmable ancillary data type registers register name bit name description r/w default anc_type 1 address: 0ah 15-8 anc_type1[15:8] used to program the did for ancillary data detection at anc output r/w 0 7-0 anc_type1[7:0] used to program the sdid for ancillary data detection at anc output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 2 address: 0bh 15-8 anc_type2[15:8] used to program the did for ancillary data detection at anc output r/w 0 7-0 anc_type2[7:0] used to program the sdid for ancillary data detection at anc output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 3 address: 0ch 15-8 anc_type3[15:8] used to program the did for ancillary data detection at anc output r/w 0 7-0 anc_type3[7:0] used to program the sdid for ancillary data detection at anc output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 4 address: 0dh 15-8 anc_type4[15:8] used to program the did for ancillary data detection at anc output r/w 0 7-0 anc_type4[7:0] used to program the sdid for ancillary data detection at anc output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 5 address: 0eh 15-8 anc_type5[15:8] used to program the did for ancillary data detection at anc output r/w 0 7-0 anc_type5[7:0] used to program the sdid for ancillary data detection at anc output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 36 of 71 proprietary & confidential 3.9.4 edh flag detection as described in section 3.9.3 , the GS9091B can detect edh packets in the received data stream. the edh flags for ancillary data, active picture, and full field areas are extracted from the detected edh packets and placed in the edh_flag_in register at address 02h ( table 3-5 ). when the edh_flag_update bit in the data_format register 04h ( table 3-7 ) is set high, the GS9091B will update the ancillary data , full field, and active picture edh flags according to smpte rp165. the updated edh flags are available in the edh_flag_out register at address 03h ( table 3-6 ). the edh packet output from the device will contain the updated flags. one set of flags is provided for both fields 1 and 2. field 1 flag data will be overwritten by field 2 flag data. when edh packets are not detected, the ues flags in the edh_flag_out register will be set high to signify that the received signal does not support error detection and handling. in addition, the edh_detect bit will be set low. these flags are set regardless of the setting of the edh_flag_update bit. edh_flag_out and edh_flag_update may be read by the host interface at any time during the received frame except on the lines defined in smpte rp165, where these flags are updated. the GS9091B will indicate the cr c validity for both active picture and full field crcs. the ap_crc_v bit in the data_format register indicates the active picture crc validity, and the ff_crc_v bit indica tes the full field crc validity (see table 3-7 ). when edh_detect = low, these bits will be cleared. the edh_flag_out and edh_flag_update register values remain set until overwritten by the decoded flags in the next received edh packet in the following field. when an edh packet is not detected during vertical blanking, the flag registers will be cleared at the end of the vertical blanking period.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 37 of 71 proprietary & confidential table 3-5: host interface description for edh flag registers register name bit name description r/w default edh_flag_in address: 02h 15 C not used C C 14 anc-ues_in ancillary unknown error status flag r 0 13 anc-ida_in ancillary internal device error detected already flag. r 0 12 anc-idh_in ancillary internal device error detected here flag. r 0 11 anc-eda_in ancillary error detected already flag. r 0 10 anc-edh_in ancillary error detected here flag. r 0 9 ff-ues_in full field unknown error status flag. r 0 8 ff-ida_in full field internal device error detected already flag. r 0 7 ff-idh_in full field internal device error detected here flag. r 0 6 ff-eda_in full field error detected already flag. r 0 5 ff-edh_in full field error detected here flag. r 0 4 ap-ues_in active picture unknown error status flag. r 0 3 ap-ida_in active picture internal device error detected already flag. r0 2 ap-idh_in active picture internal device error detected here flag r0 1 ap-eda_in active picture error detected already flag. r 0 0 ap-edh_in active picture error detected here flag. r 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 38 of 71 proprietary & confidential table 3-6: host interface description for edh flag registers register name bit name description r/w default edh_flag_out address: 03h 15 C not used C C 14 anc-ues ancillary unknown error status flag r 0 13 anc-ida ancillary internal device error detected already flag. r 0 12 anc-idh ancillary internal device error detected here flag. r 0 11 anc-eda ancillary error detected already flag. r 0 10 anc-edh ancillary error detected here flag. r 0 9 ff-ues full field unknown error status flag. r 0 8 ff-ida full field internal device error detected already flag. r 0 7 ff-idh full field internal device error detected here flag. r 0 6 ff-eda full field error detected already flag. r 0 5 ff-edh full field error detected here flag. r 0 4 ap-ues active picture unknown error status flag. r 0 3 ap-ida active picture internal device error detected already flag. r0 2 ap-idh active picture internal device error detected here flag r0 1 ap-eda active picture error detected already flag. r 0 0 ap-edh active picture error detected here flag. r 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 39 of 71 proprietary & confidential 3.9.5 smpte 352m payload identifier the GS9091B can receive and detect the presence of the smpte 352m payload identifier. upon detection of this packet, the device will extract the four words contained in the packet to the video_format_out_a and video_format_out_b registers at addresses 10h and 0fh ( table 3-8 ). the device will also indicate the version of the payload packet in bit 7 of the data_format register ( table 3-7 ). when bit 7 is set high the received smpte 352m packet is version 1, otherwise it is version 0. the video_format registers will only be updated if the received checksum is the same as the locally calculated checksum. if the device loses lock to the input data stream (locked = low), or if the smpte_bypass pin is asserted low, the video_format_out_a and video_format_out_b registers will be clea red to zero, indicating an undefined format. this is also the default setting after a device reset. table 3-7: host interface desc ription for data format register register name bit name description r/w default data_format address: 04h 15-12 C not used C C 11 edh_flag_update when set high by the application layer, the device will update the ancillary data, full field, and active picture edh flags according to smpte rp165. r/w 0 10 ap_crc_v active picture crc valid bit. r 0 9 ff_crc_v full field crc valid bit. r 0 8 edh_detect set high by the device when edh packets are detected in the incoming video data. r0 7 version_352m indicates whether decoded smpte 352m packet is version 0 or version 1. see section 3.9.5 . r0 6-5 C not used C C 4 std_lock standard lock bit. this bit will be set high when the flywheel has achieved full synchronization to the received video standard. see section 3.9.6 . r0 3-0 data_format[3:0] displays the data format being carried on the serial digital interface. see section 3.9.6.1 . r0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 40 of 71 proprietary & confidential 3.9.6 automatic video standard and data format detection the GS9091B can detect the inpu t video standard and data fo rmat by using the timing parameters extracted from the received trs id. total samples per line, active samples per line, total lines per frame, and active lines per field are all calculated and presented to the host interface via the raster_structure registers ( table 3-9 ). also associated with the ra ster_structure registers is the std_lock status bit. the GS9091B will set std_lock high when the flywheel has achieved full synchronization to the received video standard. std_lock is stored in the data_format register ( table 3-7 ). the four raster_structure registers, as we ll as the std_lock status bit will default to zero after a device reset, or if the device loses lock to the input data stream (locked = low). table 3-8: host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_out_b address: 10h 15-8 smpte 352m byte 4 data will be available in this register when video payload identification packets are detected in the data stream. r0 7-0 smpte 352m byte 3 data will be available in this register when video payload identification packets are detected in the data stream. r0 video_format_out_a address: 0fh 15-8 smpte 352m byte 2 data will be available in this register when video payload identification packets are detected in the data stream. r0 7-0 smpte 352m byte 1 data will be available in this register when video payload identification packets are detected in the data stream. r0 table 3-9: host interface descript ion for raster structure registers register name bit name description r/w default raster_structure1 address: 11h 15-11 C not used C C 10-0 raster_structure1[10:0] total lines per frame r 0 raster_structure2 address: 12h 15-13 C not used C C 12-0 raster_structure2[12:0] total words per line r 0 raster_structure3 address: 13h 15-13 C not used C C 12-0 raster_structure3[12:0] words per active line r 0 raster_structure4 address: 14h 15-11 C not used C C 10-0 raster_structure4[10:0] active lines per field r 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 41 of 71 proprietary & confidential 3.9.6.1 data format indication the GS9091B can extract the data format being ca rried on the serial di gital interface (i.e. sdti, sdi, or dvb-asi). this information is represented by bits 0 to 3 of the data_format register ( table 3-7 ). data_format[3:0] regist er codes are shown in table 3-10 . the data_format[3:0] register defaults to fh (undefined) after a system reset. the register will also be set to it s default value if the device is not locked (locked = low), or if both smpte_bypass and dvb_asi pins are low. 3.9.7 error detection and indication the GS9091B contains a number of error dete ction functions to en hance operation of the device when operating in smpte mode. thes e functions, except lock error detection, will not be available in dvb-asi mode ( section 3.7 ) or data-through mode ( section 3.8 ). the error_status register is at address 01h ( table 3-11 ). all bits, except the lock_err bit, will be cleared at the start of each video field or when read by the host interface, whichever condition occurs first. all bits, with the exception of the lock_err, will also be cleared if a change in the video standard is detected, if the device loses lock to the input data stream (locked = low), or if the smpte_bypass pin is asserted low. the error_status register, including the lock_err bit, will be set low during a system reset (reset = low). table 3-10: data format register codes data format[3:0] data format applicable standards 0h sdti dvcpro - no ecc smpte 321m 1h sdti dvcpro - ecc smpte 321m 2h sdti dvcam smpte 322m 3h sdti cp smpte 326m 4h other sdti fixed block size C 5h other sdti variable block size C 6h sdi C 7h dvb-asi C 8h ~ eh reserved C fh unknown data format C
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 42 of 71 proprietary & confidential the error_mask register ( table 3-12 ) is available to indivudally mask each error type in the error_status register. each error ty pe may be individually masked by setting its corresponding bit high. the bits of the error_mask register will default to '0' after a device reset, thus allowing all error types to be detected. the data_error signal pin indicates the status of the error_status register. this output pin is an inverted logical or of each error status flag stored in the error_status register. data_error will be set low by the device when an error condition that has not been masked is detected. table 3-11: host interface description for error status register register name bit name description r/w default error_status address: 01h 15-7 C not used C C 6 vd_std_err video standard error flag. set high when a mismatch between the received smpte 352m packets (version 1 or version 0) and the calculated video standard occurs. r0 5 ff_crc_err full field crc error flag. set high when a full field (ff) crc mismatch has been detected in field 1 or 2 r0 4 ap_crc_err active picture crc error flag. set high when an active picture (ap) crc mismatch has been detected in field 1 or 2. r0 3 lock_err lock error flag. set high whenever the locked pin is low (indicating the device is not correctly locked). r0 2 cs_err checksum error flag. set high when ancillary data packet checksum error has been detected. r0 1 sav_err start of active vide o error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. r0 0 eav_err end of active video error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. r0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 43 of 71 proprietary & confidential 3.9.7.1 video standard error detection if a mismatch between the decoded smpt e 352m packets and th e calculated video standard occurs, the GS9091B will indicate a video standa rd error by setting the vd_std_err bit of the error_status register high. the device will detect errors in both version 1 and ve rsion 0 352m packets. 3.9.7.2 edh crc error detection the GS9091B calculates the full field (ff) an d active picture (ap) crc words according to smpte rp165 in support of error detect ion and handling packets in sd signals. these calculated crc values are compared with the received crc values. if a mismatch is detected, the error is flagged in the ap _crc_err and/or ff_crc_err bits of the error_status register. these two flags are shared between fields 1 and 2. the ap_crc_err bit will be set high when an active picture crc value mismatch has been detected in field 1 or 2. the ff_crc_err bit will be set high when a full field crc value mismatch has been detected in field 1 or 2. edh crc errors will only be indicated when the device has correctly received edh packets. smpte rp165 specifies the calculation ranges and scope of edh da ta for standard 525 and 625 component digital interfaces. the GS9091B will utilize these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, the ranges will be based on the line and pixel ranges programmed by the host interface. in the absence of user-programmed calculation ranges, the ranges will be determined from the received trs timing information. the registers available to the host interf ace for programming edh calculation ranges include active picture and full field line/pixel start and end positions for both fields ( table 3-13 ). these registers default to '0' after a device reset. table 3-12: host interface descr iption for error mask register register name bit name description r/w default error_mask address: 25h 15-7 C not used C C 6 5 vd_std_err_mask video standard error flag mask bit. r/w 0 ff_crc_err_mask full field crc error flag mask bit. r/w 0 4 ap_crc_err_mask active picture crc error flag mask bit r/w 0 3 lock_err_mask lock erro r flag mask bit. r/w 0 2 cs_err_mask checksum error flag mask bit. r/w 0 1 sav_err_mask start of active video error flag mask bit. r/w 0 0 eav_err_mask end of active video error flag mask bit. r/w 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 44 of 71 proprietary & confidential if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel generated timing. the first active and full field pixel will always be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixel befo re the start of the eav trs code words. table 3-13: host interface description for edh calculation range registers register name bit name description r/w default ap_line_start_f0 address: 15h 15-11 C not used C C 10-0 ap_line_start_f0[10:0] field 0 active picture start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f0 address: 16h 15-11 C not used C C 10-0 ap_line_end_f0[10:0] field 0 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_start_f1 address: 17h 15-11 C not used C C 10-0 ap_line_start_f1[10:0] field 1 active picture start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f1 address: 18h 15-11 C not used CC 10-0 ap_line_end_f1[10:0] field 1 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_start_f0 address: 19h 15-11 C not used CC 10-0 ff_line_start_f0[10:0] field 0 fu ll field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f0 address: 1ah 15-11 C not used CC 10-0 ff_line_end_f0[10:0] field 0 full field end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_start_f1 address: 1bh 15-11 C not used CC 10-0 ff_line_start_f1[10:0] field 1 fu ll field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f1 address: 1ch 15-11 C not used CC 10-0 ff_line_end_f1[10:0] field 1 full field end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_start_f0 address: 1dh 15-13 C not used CC 12-0 ap_pixel_start_f0[12:0] field 0 active picture start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 45 of 71 proprietary & confidential ap_pixel_end_f0 address: 1eh 15-13 C not used CC 12-0 ap_pixel_end_f0[12:0] field 0 active picture end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_start_f1 address: 1fh 15-13 C not used CC 12-0 ap_pixel_start_f1[12:0] field 1 active picture start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_end_f1 address: 20h 15-13 C not used CC 12-0 ap_pixel_end_f1[12:0] field 1 active picture end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_start_f0 address: 21h 15-13 C not used CC 12-0 ff_pixel_start_f0[12:0] field 0 full field start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_end_f0 address: 22h 15-13 C not used CC 12-0 ff_pixel_end_f0[12:0] field 0 full field end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_start_f1 address: 23h 15-13 C not used CC 12-0 ff_pixel_start_f1[12:0] field 1 full field start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_end_f1 address: 24h 15-13 C not used CC 12-0 ff_pixel_end_f1[12:0] field 1 full field end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 table 3-13: host interface description for edh calculation range registers (continued) register name bit name description r/w default
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 46 of 71 proprietary & confidential 3.9.7.3 lock error detection the locked pin of the GS9091B asserts high when the devi ce has correctly locked to the received data stream (see section 3.5.1 ). the GS9091B will also indicate lock error to the host inte rface when locked = low by setting the lock_err bit in the error_status register high ( table 3-11 ). 3.9.7.4 ancillary data checksum error detection the GS9091B will calculate checksums for all received ancillary data types and compare the calculated values to the received checksum words. if a mismatch is detected, the cs_err bit of the error_status register will be set high ( table 3-11 ). although the GS9091B will calculate and co mpare checksum values for all ancillary data types by default, the host interface may be programmed to check only certain types of ancillary data checksums, as described in section 3.9.2.1 . 3.9.7.5 trs error detection trs error flags are generated by the GS9091B when the received trs h timing does not correspond to the internal flywheel timing, or when the received trs hamming codes are incorrect. these errors are flagged via the sav_err an d/or eav_err bits of the error_status register ( table 3-11 ). both 8-bit and 10-bit sav and eav errors are handled by the GS9091B. note: h timing based trs errors will only be detected if the fw_en pin is set high. f & v timing errors are not detected or corrected. 3.9.8 additional smpte mode processing the GS9091B contains an addition al processing block which is available in smpte mode only. the ioproc_en pin must be set high to enable these functions. these functions, which are all enabled by default, may be enabled or disabled individually by setting bits 0 to 3 in the ioproc _disable register ( table 3-14 ). note: after a device reset, these functions will revert to their default values.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 47 of 71 proprietary & confidential table 3-14: host interface description for internal processing disable register register name bit name description r/w default ioproc_disable address: 00h 15-10 C not used CC 9 anc_pkt_ext ancillary packet extraction. when the fifo is configured for ancillary data extraction mode, the application layer must set this bit high to begin extraction. note: setting anc_pkt_ext low will not automatically disable ancillary data extraction (see section 3.10.3.1 ). r/w 0 8-7 fifo_mode[1:0] fifo mode: these bits control which mode the internal fifo is operating in (see table 3-15 ) r/w 0 6 h_config horizontal sync timing output configuration. set low for active line blanking timing. set high for h blanking based on the h bi t setting of the trs word. see figure 3-3 in section 3.6.4. r/w 0 5-4 not used. 3 illegal_remap illegal code re-mapping. correction of illegal code words within the active picture. set high to disable. the ioproc_en pin must be set high. r/w 0 2 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction insertion. set high to disable. the ioproc_en pin must be set high. r/w 0 1 anc_csum_ins ancillary data checksum insertion. set high to disable. the ioproc_en pin must be set high. r/w 0 0 trs_ins timing reference signal insertion. the device will correct trs based errors when set low (see section 3.9.8.4 ). the ioproc_en pin must also be high. set this bit high to disable. r/w 0
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 48 of 71 proprietary & confidential 3.9.8.1 illegal code remapping if the illegal_remap bit of the ioproc_disable register is set low, the GS9091B will remap all codes within the active picture between the values 3fch and 3ffh to 3fbh. all codes within the active picture area between the values 00h and 03h will be re-mapped to 04h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values. 3.9.8.2 edh crc error correction if the edh_crc_ins bit of the ioproc_disable register is set low, the GS9091B will calculate and overwrite the active picture and full field crc words into the edh data packets received by the device. additionally, when edh_crc_ins is low, the device will set the active picture and full field crc ?v? bits high in the edh packet (see section 3.9.4 ). the ap_crc_v and ff_crc_v register bits wi ll only report the receiv ed edh validity flags. edh crc calculation ranges are described in section 3.9.7.2 . note: although the GS9091B will modify and insert edh crc wo rds and edh packet checksums, the device will only update edh error flags when the edh_flag_update bit is set high (see section 3.9.4 ). 3.9.8.3 ancillary data checksum error correction if the anc_csum_ins bit of the ioproc_d isable register is set low, ancillary checksum error correct ion and insertion is enabled, and the GS9091B will calculate and overwrite ancillary data checksums for all ancillary data words by default. if the ancillary data type has been specified in the anc_type registers of the host interface (see section 3.9.2.1 ), only the checksums for the an cillary data programmed will be updated. 3.9.8.4 trs error correction if the trs_ins bit of the ioproc_disable regi ster is set low, trs error correction and insertion is enabled. in this mode, the GS9091B will calculate an d overwrite 10-bit trs code words as required. trs code word generation will be performed using the timing parameters generated by the flywheel to provide an element of noise immunity, and will only take place if the flywheel in enabled (fw_en = high). note: only h timing based errors will be corrected (see section 3.9.7.5 ).
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 49 of 71 proprietary & confidential 3.10 internal fifo operation the GS9091B contains an intern al video line-based fifo, wh ich can be programmed by the application layer to work in any of the following modes: 1. video mode, 2. dvb-asi mode, 3. ancillary data extraction mode, or 4. bypass mode the fifo can be configured to one of the four modes by using the host interface to set the fifo_mode[1:0] bits of the ioproc_disable register (see table 3-14 in section 3.9.8 ). the setting of these bits is shown in table 3-15. to enable the fifo, the fifo_en pin must be set high. additionally, if the fifo is configured for video mode or ancillary data extraction mode, the ioproc_en pin must be set high. the fifo is fully asynchronous, allowing si multaneous read and write access. it has a depth of 2048 words, which will accommodate 1 full line of sd video for both 525 and 625 standards. the fifo is 15 bits wide: 10 bits for vi deo data and 5 bits for other signals, such as h, v, f, edh_detect, and anc. 3.10.1 video mode the internal fifo is in video mode when the fifo_en and ioproc_en pins are set high, and the fifo_mode[1:0] bits in the io proc_disable register are configured to 00b. by default, the fifo_mode[1:0] bits are set to 00b by the device whenever the smpte_bypass pin is set high and the dvb_asi pin is set low (i.e. the device is in smpte mode); however, the fifo_mode[1:0] bits may be prog ramed as required. figure 3-8 shows the input and output signals of the fifo when it is configured for video mode. table 3-15: fifo configuration bit settings fifo mode fifo_mode[1:0] register setting fifo_en pin setting ioproc_en pin setting video mode 00b high high dvb-asi mode 01b high x ancillary data extraction mode 10b high high bypass mode 11b x x note: x signifies dont care. the pin is ignored and may be set high or low.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 50 of 71 proprietary & confidential figure 3-8: fifo in video mode when operating in video mode , the GS9091B will write data se quentially into the fifo, starting with the first active pixel in location zero of the memory. in this mode, it is possible to use the fifo for clock phase interchange and data alignment / delay. the extracted h, v, and f information will also be written into the fifo. the h, v, and f outputs will be timed to the video data read from the fifo (see section 3.6.4 ). the device will ensure write-side synchronization is maintained, according to the extracted pclk and flywheel timing information. full read-control of the fifo is made availa ble such that data will be clocked out of the fifo on the rising edge of the externally provided rd_clk signal. when there is a high-to-low transition at the rd_reset pin, the first pixel presented to the video data bus will be the first 000 of the sav (see figure 3-9 ). the fifo_ld pulse may be used to control the rd_reset pin. note: the rd_reset pulse should not be he ld low for more than one rd_clk cycle. figure 3-9: rd_reset pulse timing in video mode, the anc output signal will be timed to the data output from the fifo (see section 3.9.2 for more detail). wr_clk (pclk) h fifo (video mode) rd_clk application interface 10-bit video data 10-bit video data v f h v f anc anc wr_reset rd_reset internal edh_detect edh_detect 000 3ff 000 xyz y'cbcr data rd_clk rd_reset
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 51 of 71 proprietary & confidential 3.10.2 dvb-asi mode the internal fifo is in dvb-asi mode wh en the fifo_en pin is set high, and the fifo_mode[1:0] bits in the ioproc_disable register are configured to 01b. by default, the fifo_mode[1:0] bits are set to 01b by the device whenever the dvb_asi pin is set high (i.e. the device is in dvb-asi mode); however, the fifo_mode[1:0] bits may be programed as required. figure 3-10 shows the input and output signals of the fifo when it is configured for dvb-asi mode. figure 3-10: fifo in dvb-asi mode when operating in dvb-asi mode, the GS9091B 's fifo can be us ed for clock rate interchange operation. the extracted 8-bit mpeg packets will be written into the fifo at 27mhz based on the syncout signal from the internal dvb-asi decoder block. the syncout and worderr bits are al so stored in the fifo (see section 3.7.2 ). when syncout goes high, k28.5 stuffing characters have been detected and no data will be written into the fifo. data is read out of the fifo using the rd_clk pin. in dvb-asi mode, the rd_reset pin is not used. note: with the internal fifo enabled in dvb-asi mode, syncout will always be low since the k28.5 sync characters are not stored in the fifo. wr_clk (pclk gated with syncout) syncout worderr fifo (dvb-asi mode) rd_clk 8-bit mpeg data 8-bit mpeg data worderr syncout fifo_full fifo_empty internal application interface
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 52 of 71 proprietary & confidential 3.10.2.1 reading from the fifo the fifo contains internal read and write pointers used to designate which spot in the fifo the mpeg packet will be read from or written to. these internal pointers control the status flags fifo_empty and fifo_full, which are available for output on the multi-function output port pins, if so programmed (see section 3.12 ). in the case where the write pointer is originally ahead of the read pointer, the fifo_empty flag will be set high when both pointers arrive at the same address (see block a in figure 3-12 ). this flag can be used to determine when to stop reading from the device. a write and read pointer offset may be programmed in the fifo_empty_offset[9:0] register of the host interface. if an offs et value is programmed in this register, the fifo_empty flag will be set high when the read and write pointers of the fifo are at the same address, and will remain high until the write pointer reaches the programmed offset. once the pointer offset has been exceeded, the fifo_empty flag will go low (see block b in figure 3-12 ). in the case where the read pointer is originally ahead of the write pointer, the fifo_full flag will be set high when both pointers arrive at the same address (see block c in figure 3-12 ). this flag can be used to determine when to begin reading from the device. a read and write pointer offset may also be programmed in the fifo_full_offset[9:0] register of the host interface. if an offs et value is programmed in this register, the fifo_full flag will be set high when the read and write pointers of the fifo are at the same address, and will remain set high unti l the read pointer reaches the programmed offset. once the pointer offset has been exceeded, the fifo_full flag will be cleared (see block d in figure 3-12 ). gating the rd_clk using the fifo_empty flag using the asynchronous fifo_empty flag to gate rd_clk requires external clock gating circuity. the recommended circuit for this application is shown in figure 3-11 . figure 3-11: recommended circuit to gate rd_clk using the fifo_empty flag fifo_empty q q set cl r d q q set cl r d q q set cl r d rd_clk gated rd_clk fifo_empty gated rd_clk rd_clk
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 53 of 71 proprietary & confidential figure 3-12: reading from the fifo in dvb-asi mode fifo_empty address read pointer exmple 2: fifo empty flag operation when fifo_empty[9:0] = 3ffh write pointer fifo 1023 2047 0 fifo_empty read pointer write pointer exmple 1: fifo empty flag operation when fifo_empty[9:0] = 0h 0 2047 fifo address fifo 2047 5 read pointer address write pointer fifo_full fifo exmple 3: fifo full flag operation when fifo_full[9:0] = 0h fifo_full write pointer read pointer exmple 4: fifo full flag operation when fifo_full[9:0] = 3ffh 2047 1023 0 address a c b d
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 54 of 71 proprietary & confidential 3.10.3 ancillary da ta extraction mode the internal fifo is ancillary data extraction mode when the fifo_en and ioproc_en pins are set high, and the fifo_mode[1:0] bits in the ioproc_disable register are configured to 10b. once the fifo enters ancilla ry data extraction mode, it takes 2200 pclks (82us) to initialize the fifo before anci llary data extraction can begin. in this mode, the fifo is divided into two separate blocks of 1024 words each. this allows ancillary data to be written to one si de of the fifo and from the other. thus, in each half of the fifo, the GS9091B will write the contents of the packets up to a maximum of 1024 8-bit words. as described in section 3.9.2.1 , up to five specific types of ancillary data to be extracted can be programmed in the anc_type registers. if the anc_type registers are all set to zero, the device will extract all types of ancillary data. the entire packet, including the ancillary data flag (adf), data id entification (did), secondary data identification (sdid), data count (dc), and checksum word will be written into the memory. the device will detect ancillary data packet did's placed anywhere in the video data stream, including the active picture area. additionally, the lines from which the packets are to be extracted from can be programmed into the anc_line_a[10:0] an d anc_line_b[10:0] registers, allowing ancillary data from a maximum of two lines per frame to be extracted. if only one line number register is programmed (with the othe r set to zero), ancilla ry data packets will be extracted from one line per frame only. when both registers are set to zero, the device will extract packets from all lines. the extracted ancillary data is read through the host interface starting at address 02ch up to 42bh inclusive ( 1024 words). this must be done whil e there is a valid video signal present at the serial input and the device is locked (locked = high). 3.10.3.1 ancillary data extraction and reading to start ancillary data extraction, the anc_pkt_ext bit of the ioproc_disable register must be set high (see table 3-14 in section 3.9.8 ). packet extraction will begin in the following frame after this bit has been set high. note: ancillary data ex traction will not begin until 2200 pclks (82us) after the device has entered into ancillary data extraction mode (fifo_mode[1:0] = 10b), regardless of the setting of the anc_pkt_ext bit. when the fifo is configured for ancillary data extraction mode, setting the ioproc_en pin low will disable packet extraction. if ioproc_en is low, the setting of the anc_pkt_ext host interfac e bit will be ignored. clearing the anc_pkt_ext bit will not automatically disable ancillary data extraction. to disable ancillary da ta extraction, switch the fifo into bypass mode by setting fifo_mode[1:0] = 11b. 2200 pclk cycles af ter the device re-ente rs ancillary data extraction mode, data extraction will comm ence immediately if anc_pkt_ext is still high.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 55 of 71 proprietary & confidential the anc output flag available on the i/o output pin (see section 3.12 ) can be used to determine the length of the ancillary data extracted and when to begin reading the extracted data from memory. recall that anc is high whenever ancillary data has been detected. in addition, the data count (dc) word, which is locate d three words after the ancillary data flag (adf) in the memory, can be read to determine how many valid user data words (udw) are present in the extracted pa cket (see smpte 291m for more details). the dc value can then be used to preset how many address reads must be performed to obtain only the user data words. ancillary data will be written in to the first half of the fifo until it is full or until the anc_data_switch bit is toggled (i.e. a high -to-low or low-to-high transition). if the anc_data_switch bit is not toggled, extracted data will not be written into memory after the first half of th e fifo is full (see block a in figure 3-13 ). when the anc_data_switch bit is toggled, new extracted data will be written to the second half starting at address zero (see block b in figure 3-13 ). the data in the first half of the fifo may still be read. once the data in the first half of the fifo has been read, the anc_data_switch may be toggled again to enable the second half of the fifo to be read. the first half of the fifo will be cleared, and the device will cont inue to write ancillary data to the second half of the fifo (see block c in figure 3-13 ). if the anc_data_switch bit is toggled again, new extracted data will be written to the first half starting at address zero (see block d in figure 3-13 ). the data in the second half of the fifo may still be read. toggling anc_data_switch again will clear th e second half of the fifo and restore the read and write pointers to the situation shown in block a. the switching process (shown in blocks a to d in figure 3-13 ) will continue with each toggle of the anc_data_switch bit. note: at least 1100 pclk cycles (41us) must pass between toggles of the anc_data_switch bit. also, the anc_data_switch bit must be toggled at a point in the video where no extraction is occurring (i.e. the anc signal is low). by default, the ancillary data is not remo ved from the video stream. if desired, the ancillary data may be deleted from the video stream after extraction by setting the anc_data_delete bit of the host interface hi gh. in this case, a ll existing ancillary data will be removed and replaced with bl anking values. if any of the anc_type registers are programmed with a did and/or a did and sdid, only the ancillary data packets with the matching id's will be deleted from the video stream. note: after the ancillary data determined by the anc_type registers has been deleted, other existing ancillary data may not be contiguous. the device will not concatenate the remaining ancillary data.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 56 of 71 proprietary & confidential figure 3-13: ancillary data extraction and reading 3.10.4 bypass mode the internal fifo is in bypa ss mode when the fifo_en or ioproc_en pin is set low, or the fifo_mode[1:0] bits in the ioproc_disable register are configured to 11b. by default, the fifo_mode[1:0] bits are set to 11b by the device whenever both the smpte_bypass and dvb_asi pins are low; however, the fifo_mode[1:0] bits may be programed as required. in bypass mode, the fifo is not inserted into the video path and data is presented to the output of the device synchronously with the pclk output. the fifo will be disabled and placed in static mode to save power. %% anc_data_switch = high anc_data_switch bit is toggled high. new ancillary data is written to second half of fifo starting at adress zero. application layer continues to read from the first half of the fifo. application layer read pointer internal write pointer 0 1023 1023 0 application layer read pointer internal write pointer 0 0 1023 1023 anc_data_switch = low 0 1023 internal write pointer application layer read pointer anc_data_switch = high 0 1023 anc_data_switch bit is toggled high. new ancillary data is written to first half of fifo starting at address zero. application layer continues to read from second half of fifo. toggling anc_data_switch back low will clear the second half of the fifo and go back the situation depicted in box a. application layer read pointer internal write pointer %% 0 anc_data_switch = low 1023 0 1023 anc_data_switch toggled low. first half of fifo cleared and ancillary data read from second half of fifo. device continues to write ancillary data to second half of fifo. a b c d anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data note: at least 1100 pclk cycles must pass between toggles of the anc_data_switch bit. the bit must be toggled at a point where no extraction is occuring (i.e. the anc signal is low).
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 57 of 71 proprietary & confidential 3.11 parallel data outputs the parallel data outputs are clocked out of th e device on the rising edge of pclk as shown in figure 3-14 . figure 3-14: pclk to data & control signal output timing the output data format is defined by the settings of the external smpte_bypass and dvb_asi pins (see table 3-16 ). in manual mode, these pins are set as inputs to the device. in auto mo de, the GS9091B sets these pins as output st atus signals. 3.11.1 parallel data bus output buffers the parallel data outputs of the GS9091B are driven by high-impedance buffers that support both lvttl and lvcmos levels. these buffers use either +1.8v or +3.3v, supplied at the io_vdd and io_gnd pins. when interfacing with +5v logic levels, the io_vdd pins should be supplied with +3.3v. for a low power connection, the io_vdd pins may be connected to +1.8v. all output buffers, including the pclk output, will be in a high-impedance state when the reset signal is asserted low. 50% t oh t od v oh v ol v oh v ol v oh v ol v oh v ol control signal output dout[9:0] pclk table 3-16: parallel data output format pin settings output data format dout[9:0] smpte_bypass dvb_asi 10-bit data data low low 10-bit multiplexed sd luma / chroma high low 10-bit dvb-asi dvb-asi data low high
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 58 of 71 proprietary & confidential 3.11.2 parallel output in smpte mode when the device is operating in smpte mode (see section 3.6 ), smpte data is output on the dout[9:0] pins. 3.11.3 parallel output in dvb-asi mode when operating in dvb-asi mode (see section 3.7 ), the decoded 8-bit data words will be presented on dout[7:0]. dout7 = hout is the most significant bit of the decoded transport stream data and dout0 = aout is the least significant bit. dout9 will be configured as the dvb-asi status sign al worderr and dout8 as syncout. see section 3.7.2 for a description of these dvb-asi specific output signals. 3.11.4 parallel output in data-through mode when operating in data-through mode (see section 3.8 ), the GS9091B presents data to the output data bus without performing any decoding, descrambling, or word-alignment. 3.12 programmable mu lti-function outputs the GS9091B has a 4-pin multi-function outp ut port, stat[3:0]. each pin can be programmed to output one of the following signals: h, v, f, fifo_ld , anc, edh_detect, fifo_full, and fifo_empty. each of the stat[3:0] pins can be configured individually using the stat0_config[2:0], stat1_config[2:0], stat2_config[2:0], and stat3_config[2:0] registers. table 3-18 shows the setting of the io_config registers for each of the available output signals. table 3-17: output signals availabl e on multi-function output ports output status signal reference h section 3.6.4 v section 3.6.4 f section 3.6.4 fifo_ld section 3.9.1 anc section 3.9.2 edh_detect section 3.9.3 fifo_full section 3.10.2.1 fifo_empty section 3.10.2.1
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 59 of 71 proprietary & confidential the default setting for each io_config register depends on the configuration of the device and the internal fifo mode selected. this is shown in table 3-19 . if the programmed signal is not relevant to the current mode of operation, the output will be set to a high-impedance state. table 3-18: io_config settings function i/o io_config setting h output 000b v output 001b f output 010b fifo_ld output 011b anc output 100b edh_detect output 101b fifo_full output 110b fifo_empty output 111b table 3-19: io_config default configuration device configuration io_config register i/o function default io_config setting smpte functionality smpte_bypass = high dvb_asi = low fifo: video mode or ancillary data extraction mode stat0_config output h 000b stat1_config output v 001b stat2_config output f 010b stat3_config output fifo_ld 011b dvb-asi dvb_asi = high fifo: dvb-asi mode stat0_config output fifo_full 110b stat1_config output fifo_empty 111b stat2_config output high z 000b stat3_config output high z 000b data-through smpte_bypass = low dvb_asi = low stat0_config output high z 000b stat1_config output high z 000b stat2_config output high z 000b stat3_config output high z 000b
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 60 of 71 proprietary & confidential 3.13 GS9091B lo w-latency mode when the ioproc_en pin is set low, the GS9091B will be set into low-late ncy mode. the parallel data will be output with the minimum pclk latency possible. the fifo and all processing blocks except the descrambling and word alignment blocks will be bypassed when smpte_bypass is high. low-latency mode will also be selected when smpte_bypass is set low, regardless of the setting of the ioproc_en signal (see table 3-20 ). in dvb-asi mode, the device latenc y is less than in smpte mode. when the GS9091B is configured for low-late ncy mode, the h,v, and f output timing will be based on the incoming trs codes as shown in figure 3-14 . active line-based timing is not available and the setting of the h_config host interface bit will be ignored. figure 3-15: h,v,f timing in low-latency mode table 3-20: pin settings in low-latency mode ioproc_en setting smpte_bypass setting latency (pclk cycles) low low 9 high low 10 low high 10 high high 25 note: latency applies to parallel processing core only. y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 61 of 71 proprietary & confidential 3.14 gspi host interface the gspi, or gennum serial peripheral interfac e, is a 4-wire interface provided to allow access to the host interface of the GS9091B and/or to provide additional status information through configuration registers in the device. the gspi comprises a serial data input signal sdin, serial data output signal sdout, an active low ch ip select cs , and a burst clock sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin jtag_en is provided. when jtag_en is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pin is a non-clocked loop-through of sdin and may be connected to the sdin of another device, allowing multiple devi ces to be connected to the gspi chain. the interface is illustrated in figure 3-16 . figure 3-16: gspi application interface connection all read or write access to th e GS9091B is initiated and termin ated by the ho st processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. 3.14.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 3-17 shows the command word format and bit configurations. command words are clocked into the GS9091B on the rising edge of the serial clock sclk, which operates in a burst fashion. application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 GS9091B GS9091B cs
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 62 of 71 proprietary & confidential when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operat ion. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses from the previous data word. this facilitates multiple address writes without sending a command word for each data word. auto-increment may be used for both read and write access. 3.14.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 3-19 and figure 3-20 respectively. the timing parameters are defined in table 3-21 . when several devices are connected to the gspi chain, only one cs must be asserted during a read sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin as is. where several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. table 3-21: gspi timing parameters parameter definition specification t 0 the minimum duration of time chip select, cs , must be low before the first sclk rising edge. 1.5 ns t 1 the minimum sclk period. 12.5 ns t 2 duty cycle tolerated by sclk. 40% to 60% t 3 minimum input setup time. 1.5 ns t 4 write cycle: the minimum duration of time between the last sclk command (o r data word if the auto-increment bit is high) and the first sclk of the data word. 37.1 ns t 5 read cycle: the minimum du ration of time between the last sclk command (o r data word if the auto-increment bit is high) and the first sclk of the data word. 148.4 ns t 5 read cycle - fifo in anc extraction mode: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 222.6 ns t 6 minimum output hold time. 1.5 ns t 7 the minimum duration of time between the last sclk of the gspi transaction and when cs can be set high. 37.1 ns t 8 minimum input hold time. 1.5 ns
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 63 of 71 proprietary & confidential figure 3-17: command word format figure 3-18: data word format figure 3-19: gspi read mode timing figure 3-20: gspi write mode timing msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 sdout r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period t 5 t 6 output data hold time r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 64 of 71 proprietary & confidential 3.14.3 configuration and status registers table 3-22 summarizes the GS9091B's internal status and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than the full 16 bits of information, two or more registers may be combined at a single logical address. table 3-22: GS9091B internal registers address register name reference 00h ioproc_disable section 3.9.8 01h error_status section 3.9.7 02h edh_flag_in section 3.9.4 03h edh_flag_out section 3.9.4 04h data_format section 3.9.6.1 05h io_config section 3.12 06h fifo_empty_offset section 3.10.2.1 07h fifo_full_offset section 3.10.2.1 08h - 0eh anc_type section 3.9.2 11h - 14h raster_structure section 3.9.6 15h - 24h edh_calc_ranges section 3.9.7.2 25h error_mask section 3.9.7 28h fifo_ld_position section 3.9.1.1 02ch - 42bh internal fifo section 3.10.3
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 65 of 71 proprietary & confidential 3.15 jtag operation when the jtag_en pin is set high, the host interface port (as described in section 3.14 ) will be configured for jtag test operation. in this mode, pins j4, k5, j5, and k6 become tms, tck, tdo, and tdi respectively. in addition, the reset pin will operate as the test reset pin, as well as resetting the internal registers. boundary scan testing using the jtag interface will be possible in this mode. there are two methods in which jtag can be used on the GS9091B: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applicat ions such as system power self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with tri-state buffers used in conjunction with the jtag_en input signal. this is shown in figure 3-21 . alternatively, if the test capabilities are to be used in the system, the host may still control the jtag_en input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 3-22 . figure 3-21: in-circuit jtag figure 3-22: system jtag application host GS9091B cs_tms sclk_tck sdin_tdi sdout_tdo jtag_en in-circuit ate probe application host GS9091B cs_tms sclk_tck sdin_tdi sdout_tdo jtag_en in-circuit ate probe tri-state
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 66 of 71 proprietary & confidential 3.16 device power up the GS9091B has a recommended power supply sequence. to ensure correct power up, power the core_vdd pins before the io_vdd pins. in order to initialize all internal operating conditions to their default state the application layer must hold the reset pin low for a minimum of t reset = 1ms. (see figure 3-23 ) device pins can be driven prior to power up without causing damage. figure 3-23: reset pulse core_vdd reset t reset +1.71v +1.8v reset reset t reset
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 67 of 71 proprietary & confidential 4. references & relevant standards smpte 125m component video signal 4:2:2 C bit parallel interface smpte 259m 10-bit 4:2:2 component and 4f sc composite digital signals - serial digital interface smpte 291m ancillary data packet and space formatting smpte 293m 720 x 483 active line at 59.94 hz progressive scan production C digital representation smpte 305.2m serial data transport interface smpte 352m video payload identification for digital television interfaces smpte rp165 error detection checkwords and status flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval switching point for synchronous video switching
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 68 of 71 proprietary & confidential 5. application information 5.1 typical application circuit c47 1u jtag_hostb lf+ a1 lf- b1 eq_gnd e1 sdi f1 sdi g1 ter m e2 eq_vdd h1 agc+ j1 agc- k1 eq_by pass j2 dout9 a10 dout8 b10 dout7 c10 dout6 d10 dout5 e10 dout4 f10 dout3 g10 dout2 h10 dout1 j10 dout0 k10 auto/man a7 smpte_by pass b8 dvb_asi b9 vbg a5 fifo_en a6 core_vdd b7 ioproc_en k3 jtag/host j3 cs_tms j4 sdout_tdo j5 sdin_tdi k6 sclk_tck k5 stat0 k7 stat1 k8 stat2 j8 stat3 j9 pclk a9 reset k4 locked a8 data_error j7 heat_sink_gnd f2 heat_sink_gnd f3 heat_sink_gnd g2 heat_sink_gnd g3 heat_sink_gnd h2 heat_sink_gnd h3 core_gnd d4 core_gnd d5 core_gnd e4 core_gnd e5 core_gnd f4 core_gnd f5 core_gnd g4 core_gnd g5 io_gnd d6 io_gnd d7 io_gnd e6 io_gnd e7 io_gnd f6 io_gnd f7 io_gnd g6 io_gnd g7 io_vdd c8 io_vdd e9 io_vdd f9 io_vdd h8 fw_en b6 core_vdd j6 lb_cont a3 pll_vdd b2 pll_gnd b3 vco_vdd a4 vco_gnd b4 nc a2 nc b5 nc c3 nc c4 nc c5 nc c6 nc c7 nc c9 nc d3 nc d8 nc d9 nc e3 nc e8 nc f8 nc g8 nc g9 nc h4 nc h5 nc h6 nc h7 nc k2 rd_clk k9 rd_reset h9 ana_vdd c1 ana_vdd c2 ana_gnd d1 ana_gnd d2 u4 gs9091 c38 10n c39 1u gnd_a r14 75 l1 6.2n eq_gnd c37 1u 1 tp4 r13 75 1 tp3 r15 37r4 1 tp2 c36 1u 1 3 2 jp3 bnc 1 tp1 eq_gnd gnd_d r10 0 eq_gnd c16 10n c24 10n r9 0 +3.3v c18 1u c22 1u eq_gnd gnd_d gnd_d eq_vcc j8 dvb_asi j9 r22 1k j11 smpte_by passb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 jp2 sqt-105-01-f-d-ra gnd_d j10 gnd_d io_vdd auto_manb jtag_hostb ioproc_en fifo_en fw_en control signals r23 1k j7 gnd_d j3 gnd_d j4 j5 j6 1 2 3 4 5 6 7 8 9 10 jp4 header 5x2 gnd_d +1.8v_a r16 (np) gnd_d r8 0 c42 (np) c13 10n gnd_d r18 (np) c17 10n c44 (np) dout9 r7 0 r17 (np) c43 (np) +1.8v c14 1u c15 1u gnd_a dout8 j2 dout7 eq_by pass c35 (np) c33 (np) c34 4n7 dout6 +1.8v_a dout5 c23 10n gnd_a gnd_a c21 1u dout4 io_vdd io_vdd c48 10n 9 8 14 7 u2d 74lvc04apwr resetb r1 100r 13 12 14 7 u2f 74lvc04apwr smpte_by passb 2 4 6 8 10 1 3 5 7 9 jp5 header 5x2 2 1 d2 green led 2 1 d1 y ellow led gnd_d resetb vref _io gnd_d 1 2 14 7 u2a 74lvc04apwr dout3 3 4 14 7 u2b 74lvc04apwr 5 6 14 7 u2c 74lvc04apwr r2 100r r3 100r r5 100r data_errorb gnd_d device status io_vdd +3.3v c3 100n 11 10 14 7 u2e 74lvc04apwr gnd_d dvb_asi dout2 2 1 d3 y ellow led 2 1 d4 red led locked dout1 dout0 gnd_d +1.8v c19 10n pclk r21 100k r20 100k r19 100k io_vdd c20 10n gnd_d csb_tms sdout_tdo sdin_tdi gnd_d c31 10n c32 1u io_vdd r24 1k r25 1k r26 1k sclk_tck c29 10n c30 1u c27 10n c28 1u c25 10n c26 1u eq_by pass auto_manb r28 0 smpte_by passb dvb_asi eq_gnd fifo_en c45 1u io_vdd s1 b3s-1002 c46 10n r27 1k gnd_d gnd_d fw_en ioproc_en gnd_a gnd_a r11 (np) +1.8v_a c40 100n r12 100k resetb eq_gnd locked data_errorb c41 1u note: for dvb_asi functionality, please refer to section 3.7 for the additional recommended application circuit.
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 69 of 71 proprietary & confidential 6. package & ordering information 6.1 package dimensions * the ball diameter, ball pitch, stand-off & package thickness are different from jedec spec m0192 (low profile bga family) bottom view top view 11 0.10 9.00 1.00 11 0.10 9.00 1.00 10987654321 a b c d e f g h j k h k j d f g e c b a 10 9 8 7 6 5 4 23 1 p in 1 corner pin 1 corner -a- 0.20(4x) -b- ?0.25 s c a b ?0.10 s c ?0.40~0.60(100x) 0.25 c 0.700.05 (0.61) -c- seating plane 0.15 0.30~0.50 1.71 ref. ball pitch : ball diameter : mold thickness : substrate thickness : 1.00 0.50 0.61 0.70
GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 70 of 71 proprietary & confidential 6.2 packaging data 6.3 marking diagram 6.4 ordering information parameter value package type 11mm x 11mm 100 lbga moisture sensitivity level 3 junction to case thermal resistance, j-c 41.4 junction to air thermal resistance, j-a (at zero airflow) 74.5 psi, 55.2 pb-free and rohs compliant yes GS9091B xxxxe3 yyww pin 1 id GS9091B xxxxe3 yyww yyww - date code yy - 2-digit year ww - 2-digit week number xxxx - l ot/work order id part number package temperature range GS9091Bcbe3 pb-free 100-bga 0 o c to 70 o c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation ottawa design centre 232 herzberg road, suite 101 kanata, ontario k2k 2a1 canada phone: +1 (613) 270-0458 fax: +1 (613) 270-0429 united kingdom design centre north building, walden court parsonage lane, bishops stortford hertfordshire, cm23 6db great britain phone: +44 (1279) 714170 fax: +44 (1279) 714171 japan kk shinjuku green tower building 27f 6-14-1, nishi shinjuku shinjuku-ku, tokyo, 160-0023 japan phone: +81 (03) 3349 5501 fax: +81 (03) 3349 5505 email: gennum-japan@gennum.com web site: http://www.gennum.co.jp snowbush ip - a division of gennum 439 university ave. suite 1700 toronto, ontario m5g 1y8 canada phone: +1 (416) 925-5643 fax: +1 (416) 925-0581 web site: http://www.snowbush.com aguascallientes physical design center venustiano carranza 122 int. 1 centro, aguascalientes mexico cp 20000 phone: +1 (416) 848-0328 germany niederlassung deutschland stefan-george-ring 29 81929 mnchen, germany phone: +49 89 309040 290 fax: +49 89 309040 293 email: gennum-germany@gennum.com united states - western region bayshore plaza 2107 n 1st street, suite #300 san jose, ca 95131 united states phone: +1 (408) 392-9430 fax: +1 (408) 392-9404 united states - eastern region 4281 harvester road burlington, ontario l7l 5m4 canada phone: +1 (905) 632-2996 fax: +1 (905) 632-2055 ta i w a n 6f-4, no.51, sec.2, keelung rd. sinyi district, taipei city 11502 taiwan r.o.c. phone: (886) 2-8732-8879 fax: (886) 2-8732-8870 korea 8f, jinnex lakeview bldg. 65-2, bangidong, songpagu seoul, korea 138-828 phone: +82-2-414-2991 fax: +82-2-414-2998 document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GS9091B genlinx? ii 270mb/s deserializer for sdi and dvb-asi data sheet 38910 - 2 july 2008 71 of 71 71 proprietary & confidential gennum corporation assumes no liability for an y errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein do es not imply any patent license, and gennum makes no representation that the circuit o r device is free from patent infringement. all other trademarks mentioned are the properties of their respective owners. gennum and the gennum logo are registe red trademarks of gennum corporation. ? copyright 2006 gennum corporation. al l rights reserved. printed in canada. www.gennum.com gennum corporation mailing address: p.o. box 489, station a, burlington, ontario l7r 3y3 canada street addresses: 4281 harvester road, burlington, ontario l7l 5m4 canada phone: +1 (905) 632-2996 fax: +1 (905) 632-2055 email: corporate@gennum.com www.gennum.com

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